W25P243A
64K × 64 BURST PIPELINED HIGH-SPEED
CMOS STATIC RAM
Publication Release Date: August 1999
- 1 - Revision A3
GENERAL DESCRIPTION
The W25P243A is a high-speed, low-power, synchronous-burst pipelined, CMOS static RAM
organized as 65,536 × 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst
address counter supports both Pentium burst mode and linear burst mode. The mode to be
executed is controlled by the
LBO
pin. Pipelining or non-pipelining of the data outputs is controlled by
the
FT
pin. A snooze mode can reduce power dissipation.
W25P243A supports 2T/1T mode, while disable data output within one cycle in a burst read when the
device is deselected by CE2/CE3 .
This device supports 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle.
FEATURES
• Synchronous operation
• High-speed access time: 4.5/5/6 nS (max.)
• Single +3.3V power supply
• Individual byte write capability
• 3.3V LVTTL compatible I/O
• Clock-controlled and registered input
• Asynchronous output enable
• Pipelined data output capability
• Supports snooze mode (low-power state)
• Internal burst counter supports Intel burst
(Interleaved) mode & linear burst mode
• Support 2T/1T mode
• Packaged in 128-pin QFP and TQFP
BLOCK DIAGRAM
A(15:0)
DATA I/O
REGISTER
INPUT
REGISTER
CONTROL
LOGIC
REGISTER
64K X 64
CORE
ARRAY
CE(3:1)
BWE
CLK
OE
GW
ADSC
ADSP
ADV
LBO
BW(8:1) I/O(64:1)
ZZ
W25P243A
- 2 -
PIN CONFIGURATION
V
S
S
Q
/
L
B
O
A
1
5
A
1
4
A
1
3
V
D
D
V
S
S
A
1
2
A
1
1
A
1
0
A
9R
S
V
A
8A
7A
6A
5A
4A
3V
D
D
V
S
S
A
2A
1A
0Z
ZV
D
D
Q
VDDQ
I/O32
I/O31
I/O30
I/O29
I/O28
I/O27
I/O26
I/O25
I/O24
I/O23
I/O22
VSSQ
VDDQ
I/O21
I/O20
I/O19
I/O18
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
VSSQ
VDDQ
I/O11
I/O10
I/O9
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
VSSQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
5
2
3
94
04
14
24
34
44
54
64
74
84
95
05
15
35
45
55
65
75
85
96
06
16
26
36
4
V
S
S
Q
V
D
D
Q
C
E
2
/
C
E
3
V
S
S
V
D
D
/
C
E
/
B
W
8
/
B
W
7
/
B
W
6
/
B
W
5
/
O
E
C
L
K
/
B
W
E
/
G
W
/
B
W
4
/
B
W
3
V
S
S
V
D
D
/
B
W
2
/
B
W
1
/
A
D
S
C
/
A
D
S
P
/
A
D
V
1
2
8
1
2
7
1
2
6
1
2
5
1
2
4
1
2
3
1
2
2
1
2
1
1
2
0
1
1
9
1
1
8
1
1
7
1
1
6
1
1
4
1
1
3
1
1
2
1
1
1
1
1
0
1
0
9
1
0
8
1
0
7
1
0
6
1
0
5
1
0
4
1
0
3
1
1
5
VSSQ
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
I/O40
I/O41
I/O42
I/O43
VDDQ
VSSQ
I/O44
I/O45
I/O46
I/O47
I/O48
I/O49
I/O50
I/O51
I/O52
I/O53
VDDQ
VSSQ
I/O54
I/O55
I/O56
I/O57
I/O58
I/O59
I/O60
I/O61
I/O62
I/O63
I/O64
VDDQ
N
CN
C
N
C
W25P243A
Publication Release Date: August 1999
- 3 - Revision A3
PIN DESCRIPTION
SYMBOL TYPE DESCRIPTION
A0−A15 Input, Synchronous Host address
I/O1−I/O64 I/O, Synchronous Data Inputs/Outputs
CLK Input, Clock Processor host bus clock
CE1
, CE2, CE3 Input, Synchronous Chip enables
GW
Input, Synchronous Global write
BWE
Input, Synchronous Byte write enable from cache controller
BW1
−BW8 Input, Synchronous Host bus byte enables used with
BWE
OE
Input, Asynchronous Output enable input
ADV
Input, Synchronous Internal burst address counter advance
ADSC
Input, Synchronous Address status from Chip Set
ADSP
Input, Synchronous Address status from CPU
ZZ Input, Asynchronous Snooze pin for low-power state, internal pull low
LBO
Input, Static Lower address burst order
Connected to VSS: Device is in linear mode.
Connected to VDD or unconnected: Device is in non-
linear mode.
VDDQ I/O power supply
VSSQ I/O ground
VDD Power supply
VSS Ground
RSV Reserved pin, don't use these pins
NC No connection
W25P243A
- 4 -
FUNCTIONAL DESCRIPTION
The W25P243A is a synchronous-burst pipelined SRAM designed for use in high-end personal
computers. It supports two burst address sequences for Intel systems (Interleaved mode) and linear
mode, which can be controlled by the
LBO
pin. The burst cycles are initiated by
ADSP
or
ADSC
and the burst counter is incremented whenever
ADV
is sampled low.
BURST ADDRESS SEQUENCE
INTEL SYSTEM (
LBO
= VDD) LINEAR MODE (
LBO
= VSS)
A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0]
External Start Address 00 01 10 11 00 01 10 11
Second Address 01 00 11 10 01 10 11 00
Third Address 10 11 00 01 10 11 00 01
Fourth Address 11 10 01 00 11 00 01 10
The device supports several types of write mode operations.
BWE
and
BW
[8:1] support individual
byte writes. The
BE
[7:0] signals can be directly connected to the SRAM
BW
[8:1]. The
GW
signal is
used to override the byte enable signals and allows the cache controller to write all bytes to the
SRAM, no matter what the byte write enable signals are. The various write modes are indicated in the
Write Table below. Note that in pipelined mode, the byte write enable signals are not latched by the
SRAM with addresses but with data. In pipelined mode, the cache controller must ensure the SRAM
latches both data and valid byte enable signals from the processor.
TRUTH TABLE
CYCLE ADDRESS
USED CE1 CE2 CE3 ADSP ADSC ADV OE DATA WRITE*
Unselected No 1 X X X 0 X X Hi-Z X
Unselected No 0 X 1 0 X X X Hi-Z X
Unselected No 0 0 X 0 X X X Hi-Z X
Unselected No 0 X 1 1 0 X X Hi-Z X
Unselected No 0 0 X 1 0 X X Hi-Z X
Begin Read External 0 1 0 0 X X X Hi-Z X
Begin Read External 0 1 0 1 0 X X Hi-Z Read
Continue Read Next X X X 1 1 0 1 Hi-Z Read
Continue Read Next X X X 1 1 0 0 D-Out Read
Continue Read Next 1 X X X 1 0 1 Hi-Z Read
Continue Read Next 1 X X X 1 0 0 D-Out Read
Suspend Read Current X X X 1 1 1 1 Hi-Z Read
Suspend Read Current X X X 1 1 1 0 D-Out Read
Suspend Read Current 1 X X X 1 1 1 Hi-Z Read
Suspend Read Current 1 X X X 1 1 0 D-Out Read
W25P243A
Publication Release Date: August 1999
- 5 - Revision A3
Truth Table, continued
CYCLE ADDRESS
USED CE1 CE2 CE3 ADSP ADSC ADV OE DATA WRITE*
Begin Write Current X X X 1 1 1 X Hi-Z Write
Begin Write Current 1 X X X 1 1 X Hi-Z Write
Begin Write External 0 1 0 1 0 X X Hi-Z Write
Continue Write Next X X X 1 1 0 X Hi-Z Write
Continue Write Next 1 X X X 1 0 X Hi-Z Write
Suspend Write Current X X X 1 1 1 X Hi-Z Write
Suspend Write Current 1 X X X 1 1 X Hi-Z Write
Notes:
1. For a detailed definition of read/write, see the Write Table below.
2. An "X" means don't care, "1" means logic high, and "0" means logic low.
3. The OE pin enables the data output and is not sampled with the clock. All signals of the SRAM are sampled synchronously
with the bus clock except for the OE pin.
4. On a write cycle that follows a read cycle, OE must be inactive prior to the start of write cycle to allow write data to setup to
the SRAM. OE must also disable the output buffer prior to the finish of a write cycle to ensure the SRAM data hold timings
are met.
WRITE TABLE
READ/WRITE FUNCTION GW BWE
BW8
BW7
BW6
BW5
BW4
BW3
BW2
BW1
Read 1 1 X X X X X X X X
Read 1 0 1 1 1 1 1 1 1 1
Write byte 1 I/O1−I/O8 1 0 1 1 1 1 1 1 1 0
Write byte 2 I/O9−I/O16 1 0 1 1 1 1 1 1 0 1
Write byte 2, byte 1 1 0 1 1 1 1 1 1 0 0
Write byte 3 I/O17−I/O24 1 0 1 1 1 1 1 0 1 1
Write byte 3, byte 1 1 0 1 1 1 1 1 0 1 0
Write byte 3, byte 2 1 0 1 1 1 1 1 0 0 1
Write byte 3, byte 2, byte 1 1 0 1 1 1 1 1 0 0 0
Write byte 4, I/O25−I/O32 1 0 1 1 1 1 0 1 1 1
Write byte 4, byte 1 1 0 1 1 1 1 0 1 1 0
Write byte 4, byte 2 1 0 1 1 1 1 0 1 0 1
Write byte 4, byte 2, byte 1 1 0 1 1 1 1 0 1 0 0
Write byte 4, byte 3 1 0 1 1 1 1 0 0 1 1
Write byte 4, byte 3, byte 1 1 0 1 1 1 1 0 0 1 0
Write byte 4, byte 3, byte 2 1 0 1 1 1 1 0 0 0 1
Write byte 4, byte 3, byte 2, byte 1 1 0 1 1 1 1 0 0 0 0
Write byte 5, I/O33−I/O40 1 0 1 1 1 0 1 1 1 1
Write byte 5, byte 1 1 0 1 1 1 0 1 1 1 0
W25P243A
- 6 -
Write Table, continued
READ/WRITE FUNCTION GW BWE
BW8
BW7
BW6
BW5
BW4
BW3
BW2
BW1
Write byte 5, byte 2 1 0 1 1 1 0 1 1 0 1
Write byte 5, byte 2, byte 1 1 0 1 1 1 0 1 1 0 0
Write byte 5, byte 3 1 0 1 1 1 0 1 0 1 1
Write byte 5, byte 3, byte 1 1 0 1 1 1 0 1 0 1 0
Write byte 5, byte 3, byte 2 1 0 1 1 1 0 1 0 0 1
Write byte 5, byte 3, byte 2, byte 1 1 0 1 1 1 0 1 0 0 0
Write byte 5, byte 4 1 0 1 1 1 0 0 1 1 1
Write byte 5, byte 4, byte 1 1 0 1 1 1 0 0 1 1 0
Write byte 5, byte 4, byte 2 1 0 1 1 1 0 0 1 0 1
Write byte 5, byte 4, byte 2, byte 1 1 0 1 1 1 0 0 1 0 0
Write byte 5, byte 4, byte 3 1 0 1 1 1 0 0 0 1 1
Write byte 5, byte 4, byte 3, byte 1 1 0 1 1 1 0 0 0 1 0
Write byte 5, byte 4, byte 3, byte 2 1 0 1 1 1 0 0 0 0 1
Write byte 5, byte 4, byte 3, byte 2,
byte 1 1 0 1 1 1 0 0 0 0 0
Write byte 6 1 0 1 1 0 1 1 1 1 1
Write byte 6, byte 1 1 0 1 1 0 1 1 1 1 0
Write byte 6, byte 2 1 0 1 1 0 1 1 1 0 1
Write byte 6, byte 2, byte 1 1 0 1 1 0 1 1 1 0 0
..... and so on ..... ... ... ... ... ... ... ... ... ... ...
Write byte 8, byte 7, byte 6, byte 5,
byte 4, byte 2, byte 1 1 0 0 0 0 0 0 1 0 0
Write byte 8, byte 7, byte 6, byte 5,
byte 4, byte 3 1 0 0 0 0 0 0 0 1 1
Write byte 8, byte 7, byte 6, byte 5,
byte 4, byte 3, byte 1 1 0 0 0 0 0 0 0 1 0
Write byte 8, byte 7, byte 6, byte 5,
byte 4, byte 3, byte 2 1 0 0 0 0 0 0 0 0 1
Write all bytes 1 0 0 0 0 0 0 0 0 0
Write all bytes 0 x x x x x x x x x
Power Down Mode
The ZZ state is a low-power state in which the device consumes less power than in the unselected
mode. Enabling the ZZ pin for a fixed period of time will force the SRAM into the ZZ state. Pulling the
ZZ pin low for a set period of time will wake up the SRAM again. While the SRAM is in ZZ mode, data
retention is guaranteed, but the chip will not monitor any input signals except for the ZZ pin. In the
unselected mode, on the other hand, all the input signals are monitored.
W25P243A
Publication Release Date: August 1999
- 7 - Revision A3
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER RATING UNIT
Core Supply Voltage to Vss -0.5 to 4.6 V
I/O Supply Voltage to Vss -0.5 to 4.6 V
Input/Output to VSSQ Potential VSSQ -0.5 to VDDQ +0.5 V
Allowable Power Dissipation 1.0 W
Storage Temperature -65 to 150 °C
Operating Temperature 0 to +70 °C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Operating Characteristics
(VDD/VDDQ = 3.15V to 3.6V, VSS/VSSQ = 0V, TA = 0 to 70° C)
PARAMETER SYM.
TEST CONDITIONS MIN. TYP.
MAX. UNIT
Input Low Voltage VIL - -0.5 - +0.8 V
Input High Voltage VIH - +2.0 - VDD
+0.3 V
Input Leakage Current ILI VIN = VSSQ to VDDQ -10 - +10 µA
Output Leakage
Current ILO VI/O = VSSQ to VDDQ, and data
I/O pins in high-Z state defined
in truth table
-10 - + 10 µA
Output Low Voltage VOL IOL = +8.0 mA - - 0.4 V
Output High Voltage VOH IOH = -4.0 mA 2.4 - - V
Operating Current IDD TCYC ≥ min. , I/O = 0 mA - - 350 mA
Standby Current ISB Unselected mode defined in
truth table,
VIN, VIO = VIH (min.) /VIL (max.)
TCYC ≥ min.
- - 80 mA
ZZ Mode Current IZZ ZZ mode, TCYC ≥ min. - - 5 mA
Note: Typical characteristics are measured at VDD = 3.3V, TA = 25° C.
CAPACITANCE
(VDD = 3.3V, TA = 25° C, f = 1 MHz)
PARAMETER SYM. CONDITIONS MAX. UNIT
Input Capacitance CIN VIN = 0V 6 pF
Input/Output Capacitance CI/O VOUT = 0V 8 pF
Note: These parameters are sampled but not 100% tested.
W25P243A
- 8 -
AC CHARACTERISTICS
AC Test Conditions
PARAMETER CONDITIONS
Input Pulse Levels 0V to 3V
Input Rise and Fall Times 2 nS
Input and Output Timing Reference Level 1.5V
Output Load CL = 30 pF, IOH/IOL = -4 mA/8 mA
AC Test Loads and Waveform
90% 90%
2 nS
10%
2 nS
10%
RL = 50 ohm
VL = 1.5V
OUTPUT 5 pF R2
350 ohm
R1 320 ohm
3.3V
OUTPUT
30 pF
Including
Jig and
Scope
3.0V
0V
Including
Jig and
Scope
Zo = 50 ohm
(For TKHZ, TKLZ, TOHZ, TOLZ, measurement)
AC Timing Characteristics
(VDD/VDDQ = 3.15V to 3.6V, VSS/VSSQ = 0V, TA = 0 to 70° C, all timings measured in pipelined mode)
PARAMETER SYM. W25P243A-4A W25P243A-5 W25P243A-6 UNIT NOTE
MIN. MAX. MIN. MAX. MIN. MAX. nS
Address Setup Time TAS 2.0 - 2.0 - 2.0 - nS
Address Hold Time TAH 1.0 - 1.0 - 1.0 - nS
Write Data Setup Time TDS 2.0 - 2.0 - 2.0 - nS
Write Data Hold Time TDH 1.0 - 1.0 - 1.0 - nS
ADV Setup Time TADVS 2.0 - 2.0 - 2.0 - nS
ADV Hold Time TADVH 1.0 - 1.0 - 1.0 - nS
W25P243A
Publication Release Date: August 1999
- 9 - Revision A3
AC Timing Characteristics, continued
PARAMETER SYM. W25P243A-4A W25P243A-5 W25P243A-6 UNIT NOTE
MIN. MAX. MIN. MAX. MIN. MAX.
ADSP Setup Time TADSS 2.0 - 2.0 - 2.0 - nS
ADSP Hold Time TADSH 1.0 - 1.0 - 1.0 - nS
ADSC Setup Time TADCS 2.0 - 2.0 - 2.0 - nS
ADSC Hold Time TADCH 1.0 - 1.0 - 1.0 - nS
CE1, CE2, CE3 Setup Time TCES 2.0 - 2.0 - 2.0 - nS
CE1, CE2, CE3 Hold Time TCEH 1.0 - 1.0 - 1.0 - nS
GW , BWE , BWEx Setup
Time TWS 2.0 - 2.0 - 2.0 - nS
GW , BWE , BWEx Hold Time TWH 1.0 - 1.0 - 1.0 - nS
Clock Cycle Time TCYC 10 - 12 - 13.3 - nS
Clock High Pulse Width TKH 4 - 5 - 6 - nS
Clock Low Pulse Width TKL 4 - 5 - 6 - nS
Clock Access Time TKQ - 4.5 - 5 - 6 nS
Clock High to Output High-Z TKHZ 1.5 10 1.5 12 1.5 13.3 nS 1
Clock High to Output Low-Z TKLZ 0 - 0 - 0 1 nS 1
Output Hold from Clock High TKX 1.5 - 1.5 - 1.5 - nS 1
Output Enable to Output Valid TOE - 4.5 - 5 - 6 nS
Output Disable to Output High-Z
TOHZ - 4.5 - 5 - 6 nS 1
Output Enable to Output Low-Z TOLZ 0 - 0 - 0 - nS 1
ZZ Standby Time TZZS - 100 - 100 - 100 nS 2
ZZ Recover Time TZZR 100 - 100 - 100 - nS 3
Notes:
1. These parameters are sampled but not 100% tested
2. In the ZZ mode, the SRAM will enter a low-power state. In this mode, data retention is guaranteed and the clock is active.
3. ADSC and ADSP should not be accessed for at least 100 nS after chip leaves ZZ mode.
4. Configuration signals LBO and FT are static and should not be changed during operation.
W25P243A
- 10 -
TIMING WAVEFORMS
Read Cycle Timing
2d
2c
2b
2a
1a
Single Read Burst Read Unselected
TCYC
CLK
TADSS TADSH TKH TKL ADSP is blocked by CE1 inactive
TADCS TADCH ADSC initiated read
TADVS TADVH
TAS TAH
RD1 RD2 RD3
TWS TWH
TWS TWH
TCES TCEH CE1 masks ADSP
TCES TCEH
TCES TCEH
Unselected with CE2
TOE TOHZ
TOLZ TKX
TKQ
High-Z
High-Z
ADSP
ADSC
ADV
A[15:0]
GW
BWE
BW[8:1]
CE1
CE2
OE
Data-Out
Data-In
TKLZ
TKQ
Pipelined Read
Suspend Burst
DON'T CARE
UNDEFINED
CE3
CE2 / CE3 only sampled with ADSP or ADSC
3a
TKHZ
W25P243A
Publication Release Date: August 1999
- 11 - Revision A3
Timing Waveforms, continued
Write Cycle Timing
1a
Single Write Burst Write Unselected
TCYC
CLK
TADSS TADSH TKH TKL ADSP is blocked by CE1 inactive
TADCS TADCH ADSC initiated write
TADVS TADVH
TAS TAH
WR1 WR2 WR3
TWS TWH
TWS TWH
TCES TCEH CE1 masks ADSP
TCES TCEH
TCES TCEH
CE2 / CE3 only sampled with ADSP or ADSC Unselected with CE2
High-Z
High-Z
ADSP
ADSC
ADV
A[15:0]
GW
BWE
BW[8:1]
CE1
CE2
OE
Data-Out
Data-In 2a 2b 2c 2d 3a
Write
GWE allows processor address (and BE=BW)
to be pipelined during a writeback
TWS TWH
WR1 WR2 WR3
TDS TDH BW[4:1] are applied only to first cycle of WR2
ADV must be inactive for ADSP write
DON'T CARE
UNDEFINED
CE3
W25P243A
- 12 -
Timing Waveforms, continued
Read/Write Cycle Timing
ADSP is blocked by CE1 inactive
2c
2a
1a
Single Read Burst Read Unselected
TCYC
CLK
TADSS TADSH TKH TKL
TADCS TADCH ADSC initiated read
TADVS TADVH Suspend Burst
TAS TAH
RD1 WR1 RD2
TWS TWH
TWS TWH
TCES TCEH CE1 masks ADSP
TCES TCEH
TCES TCEH
TOE TOHZ
TOLZ TOH
2d
TKHZ
TKX
High-Z
High-Z
ADSP
ADSC
ADV
A[15:0]
GW
BWE
BW[8:1]
CE1
CE2
OE
Data-Out
Data-In
TKLZ
TKQ
Single Write
WR1
TWS TWH
CE2 / CE3 only sampled with ADSP or ADSC
Unselected with CE3
2b
1a
TDSTDH
DON'T CARE
UNDEFINED
CE3
W25P243A
Publication Release Date: August 1999
- 13 - Revision A3
Timing Waveforms, continued
ZZ and RD Timing
1a
Single Read Snooze -with Data Retention Read
TCYC
CLK
TADSS TADSH
TKH TKL
TADVS TADVH
TAS TAH
RD1
TWS TWH
TWS TWH
TCES TCEH
TCES TCEH
TCES TCEH
TOE TOHZ
TOLZ
High-Z
High-Z
ADSP
ADSC
ADV
A[15:0]
GW
BWE
BW[8:1]
CE1
CE2
CE3
OE
Data-Out
Data-In
TKLZ
TKQ
RD2
TKHZ
TWS TWH
RD RD
TKX
RD
TZZS TZZR
ZZ
DON'T CARE
UNDEFINED
W25P243A
- 14 -
Timing Waveforms, continued
Dual Bank Burst Read Cycle
CLK
ADSP
ADSC
ADV
GW
BWE
BW[8:1]
CE1
OE
D[63:0]
Bank 0
DON'T CARE
UNDEFINED
Select Bank 0 Select Bank 1
1d1c
1a 1b
D[63:0]
Bank 1 2d2c
2a 2b
CE[3:2]
Bank 0
CE[3:2]
Bank 1
A[31:3] Read 1 Read 2
Select Bank 0
Read 3
Active Non-
Active Active
Non-
Active
Non-
Active Activ
e
W25P243A
Publication Release Date: August 1999
- 15 - Revision A3
ORDERING INFORMATION
PART NO. ACCESS
TIME (nS) OPERATING
CURRENT
MAX. (mA)
STANDBY
CURRENT
MAX. (mA)
PACKAGE
W25P243AF-4A 4.5 350 80 128-pin QFP
W25P243AF-5 5 350 80 128-pin QFP
W25P243AF-6 6 350 80 128-pin QFP
W25P243AD-4A 4.5 350 80 128-pin TQFP
W25P243AD-5 5 350 80 128-pin TQFP
W25P243AD-6 6 350 80 128-pin TQFP
Notes
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
W25P243A
- 16 -
PACKAGE DIMENSIONS
128-pin QFP
103
128
102
65
64
39
38
1
c
Detail F
See Detail F
1
L
L
Seating Plane
1
A
A
y
E
H
E
b
e
D
D
H
A2θ
0.10
0120
0.004
1.60
1.00
17.40
0.80
17.20
0.60
17.00
0.063
0.039
0.685
0.031
0.677
0.023
0.669
0.50
14.10
0.25
0.25
2.87
3.40
14.00
2.72
13.90
0.10
0.15
2.57
0.10
0.555
0.010
0.010
0.113
0.134
0.551
0.107
0.020
0.547
0.004
0.006
0.101
0.004
Symbol Min. Nom. Max. Max.
Nom.
Min.
Dimension in inches Dimension in mm
A
b
c
D
e
HD
HE
L
y
A
A
L1
1
2
E
0.008
0.006 0.15
0.20
12
0.783 0.787 0.791 19.90 20.00 20.10
0.905 0.913 0.921 23.00 23.20 23.40
0.055 0.071 1.40 1.80
θ
W25P243A
Publication Release Date: August 1999
- 17 - Revision A3
Package Dimensions, continued
128-pin TQFP
103
128
102
65
64
39
38
1
c
Detail F
See Detail F
1
L
L
Seating Plane 1
A
A
y
E
HE
b
e
D
D
H
A
2
0.10
0120
0.004
1.00
0.75
16.10
0.60
16.00
0.45
15.90
0.039
0.030
0.634
0.024
0.630
0.018
0.626
0.50
14.10
0.25
0.27
1.45
1.60
14.00
1.40
13.90
0.10
0.15
1.35
0.05
0.555
0.010
0.011
0.057
0.063
0.551
0.055
0.020
0.547
0.004
0.006
0.053
0.002
Symbol Min. Nom. Max. Max.
Nom.
Min.
Dimension in inches Dimension in mm
A
b
c
D
e
HD
HE
L
y
A
A
L1
1
2
E
0.008
0.006 0.15
0.20
12
0.783 0.787 0.791 19.90 20.00 20.10
0.862 0.866 0.870 21.90 22.00 22.10
θ
θ
W25P243A
- 18 -
VERSION HISTORY
VERSION DATE PAGE DESCRIPTION
A1 Nov. 1997 Initial Issued
A2 Feb. 1998 1 to 5, 8 to 12, 14 Eliminate the CE2 and CE3 functionality
A3 Aug. 1999 1, 8, 9, 15 Support 83, 75 MHz
9 TOHZ: Change from "Output Enable" to "
Output Disable"
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-7197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
Note: All data and specifications are subject to change without notice.
